The present invention relates generally to a semiconductor device and method for manufacturing the same, and more specifically to a semiconductor device including an insulated gate field effect transistor (IGFET) including a gate electrode that includes polysilicon and metal or metal silicide having a high melting point and a method of manufacturing the same.
In order to improve the integration of a semiconductor device it is desirable to make smaller contact holes for a contact electrode to provide a connection between wiring layers and source/drain regions of a metal oxide semiconductor field effect transistor (MOSFET). It is also desirable to make the contact holes having improved accuracy of placement. In order to do this, a technique for forming a contact hole and electrode has been developed and is known as a self aligned contact (SAC).
Referring to FIGS. 9 and 10, cross-sectional views of a conventional manufacturing method of conventional semiconductor device having SAC technique after various processing steps are set forth.
Referring now to FIG. 9(a), gate insulating film 202 consisting of silicon oxide (such as SiO2) is formed on the surface of silicon substrate 201. A laminated film consists of poysilicon film 203, WSi (tungsten silicide) film 204, and a cap film 205 consisting of a silicon nitride (such as Si3N4) film. Using a photolithography technique, cap film 205, WSi film 204, and polysilicon film 203 are etched into a desired pattern to form gate electrode 200.
In regions other than the gate electrode, the surface of gate insulating film 202 is also etched and made thinner. Thus, the film thickness of gate insulating film 202 is increased by thermal oxidation to replace the etched portions. As illustrated in FIG. 9(b), during this step, a silicon oxide side wall film 207 is formed on the side surface of gate electrode 200.
As illustrated in FIG. 9(c), the surface of silicon substrate is subjected to ion implantion with an impurity to form source drain regions 208 with a self alignment method in which gate electrode 200 is used as a mask. In this way, a MOS type transistor is formed.
Referring now to FIG. 9(d), silicon nitride film 209 is formed with a chemical vapor deposition (CVD) method. Silicon nitride film 209 serves as an etching stopper film.
Referring now to FIG. 10(a), interlayer insulating film 210 such as a BPSG (Boro-PhosphoSilicate Glass) film is formed on the entire surface to cover gate electrode and provide a flat surface.
Referring to FIG. 10(b), a hole 212a is opened in interlayer insulating film 210 over the source/drain region 208 using a photolithography technique. When forming hole 212a, etching stopper film 209 formed on the side surface of gate electrode 200 is not etched. Only interlayer insulating film 210 composed of BPSG is etched based on a difference of a selective etching ratio between etching stopper film 209 and interlayer insulating film 210.
Referring now to FIG. 10(c), an anisotropic etching is applied to etching stopper film 209 exposed in hole 201a. Further etching is applied to gate insulating film 202. In this way, contact hole 212 is opened with a SAC technique.
Next, as illustrated in FIG. 10(d), a wiring electrode 213a is formed in contact hole 212 to provide an electrical connection between a top part of wiring electrode 213 and source/drain region 208. Because contact hole 212 is formed using a SAC technique with etching stopper film 209 on the side surface of gate electrode 200, the MOS type element can be made fine. Even if a mask for opening a contact hole is out of position, side wall film 207 is not etched due to the etching stopper film 209. Thus, upper layer electrode 204 and lower layer electrode 203 of gate electrode 200 can be prevented from being exposed in contact hole 212. Thus, a margin for positioning the mask for the contact hole 212 can be increased and yield may be improved.
FIG. 11 are cross-sectional views of a conventional manufacturing method of conventional semiconductor device having SAC technique after various processing steps are set forth. FIG. 11(a) illustrates a reduced distance between the stopper film 209 and the surface of the silicon substrate 201 in a region close to the edge of lower layer electrode 203. FIG. 11(b) illustrates an overhang in a side wall oxide layer. FIG. 11(c) illustrates a void in a BPSG interlayer insulating film.
In the formation of a contact electrode using the conventional SAC technology, a thermal oxidation step is performed as illustrated in FIG. 9(b). This thermal oxidation step is necessary because the gate insulating film 202 is partially etched and made thinner during the etching of cap film 205, upper layer electrode 204, and lower layer electrode 203 when forming the gate electrode 200. If the silicon nitride film (stopper film 209) is formed after the above-mentioned etching step without the additional thermal oxidation step, a distance between the stopper film 209 and the surface of the silicon substrate 201 in a region close to the edge of lower layer electrode 203 is reduced. This reduced distance is illustrated in FIG. 11(a) as a reduced interval t. Hot carriers are likely to be trapped in an interface between the silicon nitride film (stopper film 209) and the silicon oxide film (gate insulating film 202). This can change the value of the threshold voltage of the MOS type transistor, thus making it difficult to manufacture a MOS type transistor in accordance to the designed values. To solve this problem, the thermal oxidation step is performed as illustrate in FIG. 9(b) and the thickness of gate insulating film 202 is increased. This may prevent variations of the threshold value caused by hot carriers being trapped in the interface between the silicon nitride film (stopper film 209) and the silicon oxide film (gate insulating film 202) so that the desired characteristics of the MOS transistor can be achieved.
A technique of thermal oxidation including the side surface of the gate electrode has been proposed by the applicant and disclosed in Japanese Laid-Open Patent Publication No. 02-47871.
Thermal oxidation treatment for increasing the thickness of gate insulating film 202 causes side surfaces of the polysilicon film (lower layer electrode 203) and the WSi film (upper layer electrode 204) to be oxidized simultaneously. In this way, silicon oxide film (side wall film 207) is formed as illustrated in FIG. 9(b).
However, a silicide material, such as WSi (upper layer electrode 204) may be more likely to be oxidized than polysilicon (lower layer electrode 203) depending on the oxidation condition. Accordingly, depending upon the oxidation condition in the step illustrated in FIG. 9(b), side wall film 207 may become thicker on the side surface of upper layer electrode 204 than on the side surface of lower layer electrode 203 as illustrated with side wall film 207 in FIG. 11(b). In this case, side wall film 207 may include an overhang portion 207a that protrudes laterally from upper layer electrode 204.
When there is an overhang portion 207a protruding from a side wall film 207, the regions around the sides of gate electrode 200 are shielded during the ion implantation step as illustrated in FIG. 11(b). This can prevent regions of the source/drain region 208 near the edges of the gate electrode 200 from being sufficiently ion implanted with an impurity. This can cause an increased diffusion layer resistance of the source/drain region 208 located in the vicinity of the gate electrode 200 and adversely affect characteristics of the MOS transistor.
Also, a side wall film 207 including an overhang portion 207a on the side surface of upper layer electrode 204 can cause the CVD silicon nitride film (etching stopper film 209) in FIG. 9(d) to include a protruding portion 209a as illustrated in FIG. 11(c). Thus, when BPSG interlayer insulating film 210 is formed, the protruding portion 209a can make it difficult to fill the central region of the contact hole and a void X is likely to be formed as illustrated in FIG. 11(c). If the void X is formed in interlayer insulating film 210, a short-circuit can occur in adjacent contact holes (such as contact hole 212 in FIG. 10(c)) during the contact forming process. This reduces the yield of the product and increases manufacturing costs.
In light of the above discussion, it would be desirable to provide a semiconductor device, which may include a side wall film, such as a silicon oxide film or silicon nitride film, on the side surface of a gate electrode that may not have an overhang portion. It would also be desirable to provide an insulated gate field effect transistor (IGFET) that does not have characteristics affected by an overhang portion of a side wall film. It would also be desirable to provide a manufacturing method for the semiconductor device.
A semiconductor device according to the present embodiments may include an IGFET (insulated gate field effect transistor) and a method of manufacturing the same. The semiconductor device may include an oxide film or a nitride film provided on a side surface of a gate electrode in such a manner than an overhang condition may not occur. In this way, operating characteristics of the IGFET may not be deteriorated and voids may not appear in filling regions of an interlayer insulating film so that isolation characteristics may not be deteriorated.
According to one aspect of the embodiments, a semiconductor device may include an IGFET including a gate electrode that may include a lower layer electrode formed on a gate insulating film and an upper layer electrode formed on the lower layer electrode. A cap film may be formed on the upper layer electrode. A first nitride film may be formed on a side surface of the upper layer electrode. An oxide film may be formed on a side surface of the lower layer electrode. An etching stopper film may include a second nitride film formed on the outside of the first nitride film and oxide film.
According to another aspect of the embodiments, the first nitride film may be a thermal nitride film.
According to another aspect of the embodiments, the first nitride film may be a rapidly heated thermal nitride film.
According to another aspect of the embodiments, the first nitride film may have a thickness of approximately 2 to 5 nm.
According to another aspect of the embodiments, an interlayer insulating film may be formed to cover the gate electrode of the IGFET. A contact hole may be opened in the interlayer insulating film to expose a source/drain region of the IGFET. A conductor may fill the contact hole and be electrically connected with the source/drain region.
According to another aspect of the embodiments, the oxide film may be a thermal oxide film.
According to another aspect of the embodiments, the second nitride film may be formed with chemical vapor deposition (CVD).
According to another aspect of the embodiments, a method for manufacturing a semiconductor device including an IGFET may include the steps of forming a gate insulating film on a semiconductor substrate, forming a laminate film on the gate insulating film where the laminate film may include an insulating film formed on a second conductive film formed on a first conductive film, etching the insulating film and the second conductive film into a predetermined pattern to form a cap film and an upper layer gate electrode, forming a first nitride film on the side surface of the upper layer gate electrode, etching the first conductive film using the cap layer, upper layer gate electrode and the nitride film as a mask to form a lower layer gate electrode, forming a first oxide film on the side surface of the lower layer electrode, and forming an etching stopper film including a second nitride film over the entire surface.
According to another aspect of the embodiments, the first conductive film may be a polysilicon film and the second conductive film may be a metal film.
According to another aspect of the embodiments, the first conductive film may include a polysilicon film and the second conductive film may include a metal silicide film having a high melting point.
According to another aspect of the embodiments, the first nitride film may be a thermal nitride film and the first oxide film may be a thermal oxide film.
According to another aspect of the embodiments, forming the etching stopper film may include forming the second nitride film with a chemical vapor dposition.
According to another aspect of the embodiments, the first nitride film may be a thermal nitride film formed with a rapid thermal nitridation step using a lamp as a heat source.
According to another aspect of the embodiments, a method for manufacturing the semiconductor device may include the steps of forming a source/drain region by doping an impurity into the semiconductor substrate after the step of forming the first oxide film and forming an interlayer insulating film over the entire surface and selectively etching the interlayer insulating film with a selective etching ratio for the etching stopper film to open a contact hole after the step of forming the etching stopper film.
According to another aspect of the embodiments, a method for manufacturing the semiconductor device may include the steps of forming a lightly doped drain (LDD) region by doping a first impurity concentration into the semiconductor substrate after the step of forming the first oxide film, anisotropic etching the etching stopper film to form a side wall etching stopper film on side surfaces of the lower layer gate electrode, upper layer gate electrode, and cap layer, and forming a source/drain region by doping a second impurity concentration into the semiconductor substrate using the side wall etching stopper film as a mask. The first impurity concentration may be lower than the second impurity concentration.
According to another aspect of the embodiments, a method for manufacturing the semiconductor device may include the steps of forming a second oxide film over the entire surface of the substrate with a chemical vapor deposition method, anisotropic etching the second oxide film to form a side oxide film on the side surface of the etching stopper film, and forming the source/drain region after the step of forming the side wall.
According to another aspect of the embodiments, a semiconductor device may include a first region and a second region. A first gate electrode of a first IGFET in the first region may have a first lower layer electrode formed on a first gate insulating film and a first upper layer electrode formed on the first lower layer electrode. A first cap film may be formed on the first upper layer electrode. A first nitride film may be formed on a side surface of the first upper layer electrode. A first oxide film may be formed on a side surface of the first lower layer electrode. A first etching stopper film may include a second nitride film formed on the outside of the first nitride film and first oxide film. A second gate electrode of a second IGFET in the second region may have a second lower layer electrode formed on a second gate insulating film and a second upper layer electrode formed on the second lower layer electrode. A second cap film may be formed on the second upper layer electrode. A third nitride film may be formed on a side surface of the second upper layer electrode. A second oxide film may be formed on a side surface of the second lower layer electrode. A second etching stopper film may include a fourth nitride film formed on the outside of the third nitride film and second oxide film. The first IGFET may include a lightly doped drain.
According to another aspect of the embodiments, the semiconductor device may be a semiconductor memory device.
According to another aspect of the embodiments, the first region may be a memory cell region and the second region may be a peripheral circuit region.
According to another aspect of the embodiments, a first contact may provide an electrical connection to a first sour/drain region of the first IGFET. A second contact may provide an electrical connection to a second source/drain region of the second IGFET. A first spacing from the first contact to the first electrode may be greater than a second spacing from the second contact to the second gate electrode.